收藏本站
DSP56300 Core Functional Blocks
Stack counter register
1.6.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator,
which performs low-power division and clock pulse generation. These features allow you to:
Change the low-power divide factor without losing the lock
Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a low-frequency
clock input, a feature that offers two immediate benefits:
A lower-frequency clock input reduces the overall electromagnetic interference generated
by a system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
1.6.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems with testing
high-density circuit boards led to the development of this standard under the sponsorship of the
Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard. The test logic includes a TAP with
four dedicated signals, a 16-state controller, and three test data registers. A boundary scan
register links all device signals into a single shift register. The test logic, implemented utilizing
static logic design, is independent of the device system logic. For details on the JTAG port,
consult the DSP56300 Family Manual .
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that
you can examine registers, memory, or internal peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are provided
through the JTAG TAP signals. For details on the OnCE module, consult the DSP56300 Family
Manual .
1.6.6 Internal Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to work
with the two address ALUs and to feed two operands simultaneously to the data ALU. Memory
space includes internal RAM and ROM and can be expanded off-chip under software control.
There is an on-chip 192 x 24-bit bootstrap ROM. For details on internal memory, see Chapter 3,
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
1-9
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
DSPAUDIOEVMMB1E BOARD MOTHER DSP563XX
DSPIC30F2010 DEVELOPMENT KIT KIT DEV EMBEDDED C
DSTRM-KT-0181A DSTREAM DEBUG AND TRACE UNIT
DSUT1CSU SURGE SUPPR NETWORK W/GROUND
DTEL2 SURGE SUPPRESSOR PHONE RJ11/RJ45
DV003001 PROGRAMMER PICSTART PLUS 16C/17C
DV164035 MPLAB ICD3 IN-CIRC DEBUGGER
DV164039 KIT DEV PIC24FJ256DA210
相关代理商/技术参数
DSP56311EVMIG_D 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311EVMIG DSP56311EVM Sample Code
DSP56311EVMUM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Evaluation Module Hardware Reference Manual
DSP56311FACT 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Higher performance programmable DSP for demanding voice and data applications
DSP56311UM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 24-Bit Digital Signal Processor Users Manual
DSP56311UMAD 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Users Manual Addendum
DSP56311VF150 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/300MMACS 150Mhz EFCOP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150B1 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150R2 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT